The semiconductor far back end assembly and packaging industry is in need of a low cost packaging solution for higher interconnect density and smaller form factor for mobile and internet-of-things (IoT) applications as well as others. One existing solution is fan out wafer level chip scale packaging (FOWLCSP). While this solution has been deployed on a limited basis, it has a high cost and limited scalability. A goal with this solution is to move from a 330 millimeter (mm) diameter round substrate to a 500×500 mm square substrate for cost reduction. However, this solution also has an inherent disadvantage of handling large thin panels as well as pattern run out across the panel. Both of these disadvantages drive higher manufacturing tool costs and minimize any potential savings associated with this solution.
An example of a conventional FOWLCSP in a package on package (PoP) configuration is illustrated in FIG. 1A. PoP wafer level fan out package includes a stack package 101 and wafer level fan out package 103. Stack package 101 such as a memory or a chip size package may be coupled to an electrically conductive pattern 105 of the wafer level fan out package 103. The stack package 101 includes first and second semiconductor dies 107, 109, substrate 111, an encapsulant 113, and solder balls 115. The solder balls 115 are coupled to the electrically conductive pattern 105. Wafer level fan out package 103 further includes conductive vias 117, semiconductor die 119, and solder balls 121. Chip suppliers and mobile product manufacturers desire increased functionality of products by increasing silicon content and interconnects between silicon chips, while at the same time maintaining low costs, producing thin products with a small footprint package.
FIG. 1B is an example of a conventional fan-in wafer level package having a silicon die, 121, bump or land connections 129 and metal conductors 127. FIG. 1C is an example of a wafer level fan out package including a silicon die 121 that is typically encapsulated in an epoxy based thermoset material 123. Unlike conventional wafer level packages of FIG. 1B, where all the connections from the package to the next level of interconnect such as a system or module level printed circuit board must be contained within the area of the surface of the silicon die 121 itself, conventional fan out wafer level chip scale packaging of FIG. 1C utilizes the encapsulation material 123 as an extension onto which dielectric material 125 and metal conductors 127 can be patterned extending interconnect to next level with a larger quantity of bump or land connections 129 and/or a larger pitch between connections.
A need therefore exists for methodology enabling utilization of mature film based technology to create a thinner package at reduced cost by using lower cost manufacturing equipment and which does not depend on panel based processing that drives higher manufacturing equipment costs and results in total manufacturing costs that exceed the markets ability to pay.